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gnu: symbiyosys: Fix build.
* gnu/packages/electronics.scm (symbiyosys)[inputs]: Remove git-minimal/pinned and yosys; add yosys-clang. [arguments]<#:make-flags>: Use clang. <#:phases>: Add build and delete git-init. <#:parallel-tests?>: Disable. [home-page]: Update. [description]: Improve. [synopsis]: Typo. Change-Id: I7ce2ba0daf35b2c21df3c217ef3113e621d129cc
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1 changed files with 6 additions and 9 deletions
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@ -2348,6 +2348,7 @@ them usable as simple logic analyzer and/or oscilloscope hardware.")
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(build-system gnu-build-system)
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(arguments
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(list
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#:parallel-tests? #f
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#:test-target "test"
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#:modules `((guix build gnu-build-system)
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((guix build python-build-system) #:prefix python:)
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@ -2363,10 +2364,7 @@ them usable as simple logic analyzer and/or oscilloscope hardware.")
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;; (add-after 'install 'build-info
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;; (lambda _
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;; (invoke "make" "-C" "docs" "info")))
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(add-before 'check 'git-init
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(lambda _
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(invoke "git" "init"))) ;check expects a git repo
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(add-after 'git-init 'patch-/usr/bin/env
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(add-after 'unpack 'patch-/usr/bin/env
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* "sbysrc/sby_core.py"
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(("\"/usr/bin/env\", ")
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@ -2378,20 +2376,19 @@ them usable as simple logic analyzer and/or oscilloscope hardware.")
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(assoc-ref python:%standard-phases 'wrap)))))
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(inputs (list abc-yosyshq
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boolector
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git-minimal/pinned
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python
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python-click
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python-xmlschema
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z3
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yices
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yosys))
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yosys-clang))
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;; TODO: see above build-info phase comment.
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;; (native-inputs (list
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;; python-sphinx python-sphinx-argparse texinfo))
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(home-page "https://github.com/YosysHQ/sby/")
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(synopsis "Formal hardware verification with yosys")
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(home-page "https://yosyshq.readthedocs.io/projects/sby/en/latest/")
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(synopsis "Formal hardware verification with Yosys")
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(description
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"SimbyYosys is a front-end program for yosys-based formal hardware
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"code{Simbiyosys} is a front-end program for Yosys-based formal hardware
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verification flows.")
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(license license:isc)))
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