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gnu: Add python-hdlconvertor.
* gnu/packages/electronics.scm (python-hdlconvertor): New variable. (yosys-src-for-hdlconvertor-tests): New variable. Change-Id: I0acd8c8f050a5bc632f68511b3e7d24cf3621162
This commit is contained in:
Danny Milosavljevic
parent
1adf50f5df
commit
5dca6d6643
1 changed files with 146 additions and 0 deletions
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@ -92,6 +92,7 @@
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#:use-module (gnu packages graphviz)
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#:use-module (gnu packages gtk)
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#:use-module (gnu packages image)
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#:use-module (gnu packages java)
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#:use-module (gnu packages libedit)
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#:use-module (gnu packages libffi)
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#:use-module (gnu packages libftdi)
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@ -2205,6 +2206,151 @@ for @acronym{VHDL, Very high speed integrated circuit Hardware Description Langu
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SystemVerilog, and SystemC, with conversion between languages and to JSON.")
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(license license:expat)))
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;; Yosys source pinned to hdlConvertor v2.3 submodule commit for parsing tests.
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(define yosys-src-for-hdlconvertor-tests
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/yosys")
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(commit "a299e606f864942c7edf90c4ad3998f4f4a346cf")))
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(file-name "yosys-src-for-hdlconvertor-tests")
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(sha256
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(base32 "106bzlljn6843740r8rbaqf5ivkyfcgp25dgzds97j48ypmv6fih"))))
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(define-public python-hdlconvertor
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(package
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(name "python-hdlconvertor")
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(version "2.3")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/Nic30/hdlConvertor")
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(commit (string-append "v" version))))
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(file-name (git-file-name name version))
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(sha256
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(base32 "0xa7wm324dwp4wks8l9njpd2bz4gn7dfygdc3a78lxy1prvzbyyz"))))
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(build-system pyproject-build-system)
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(arguments
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(list
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#:test-flags
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;; Ignore tests inside yosys source tree (they're unrelated yosys tests).
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#~(list "--ignore=tests/yosys")
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#:phases
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#~(modify-phases %standard-phases
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(add-before 'build 'setup-antlr
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(lambda* (#:key inputs #:allow-other-keys)
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;; Build classpath from input jars.
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(let* ((st4 (search-input-file inputs
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"share/java/java-stringtemplate-4.0.8.jar"))
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(antlr4 (search-input-file inputs
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"share/java/antlr4.jar"))
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(antlr4-rt (search-input-file inputs
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"share/java/java-antlr4-runtime.jar"))
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(antlr3 (search-input-file inputs
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"share/java/antlr3-3.5.2.jar"))
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(treelayout (search-input-file inputs
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"share/java/java-treelayout-1.0.3.jar"))
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(classpath (string-join (list st4 antlr4 antlr4-rt
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antlr3 treelayout)
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":"))
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(antlr4cpp-include (search-input-directory
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inputs "include/antlr4-runtime"))
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(antlr4cpp-lib (search-input-file
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inputs "lib/libantlr4-runtime.so"))
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(python-include (search-input-directory
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inputs "include/python3.11")))
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;; Patch CMake to use our paths directly.
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(substitute* "src/CMake_antlr4.txt"
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(("set\\(ANTLR_CLASSPATH \"\"\\)")
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(string-append "set(ANTLR_CLASSPATH \"" classpath "\")"))
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;; Skip the jar search loop.
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(("FOREACH\\(antlr_jar \\$\\{ANTLR_JARS\\}\\)")
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"FOREACH(antlr_jar )")
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;; Set C++ runtime paths before find commands.
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(("# search for antlr4 include dir and library")
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(string-append
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"# search for antlr4 include dir and library\n"
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"set(ANTLR4CPP_INCLUDE_DIRS \"" antlr4cpp-include "\")\n"
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"set(ANTLR4CPP_LIBRARIES \"" antlr4cpp-lib "\")\n")))
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;; hdlConvertor/CMakeLists.txt is a sibling subdirectory to src/
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;; so variables set in src/CMake_antlr4.txt aren't visible here;
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;; inject both ANTLR and Python include paths before
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;; include_directories.
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(substitute* "hdlConvertor/CMakeLists.txt"
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(("include_directories\\(")
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(string-append
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"set(ANTLR4CPP_INCLUDE_DIRS \"" antlr4cpp-include "\")\n"
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"set(PYTHON_INCLUDE_DIRS \"" python-include "\")\n"
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"include_directories(")))
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;; ANTLR4 4.10+ changed from .as<T>() to std::any_cast<T>().
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;; Upstream fixed this in commit 8b07c10 using preprocessor
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;; conditionals to support both old and new APIs, but that
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;; commit also includes unrelated changes (Block statement
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;; support). We apply a simplified fix for ANTLR 4.10+
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;; only.
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(substitute* "src/verilogPreproc/verilogPreproc.cpp"
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(("visitMacro_call\\(mc, false\\)\\.as<string>\\(\\)")
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"std::any_cast<string>(visitMacro_call(mc, false))")
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(("params = visitDefine_args\\(da\\);")
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(string-append "params = std::any_cast<"
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"vector<MacroDefVerilog::param_info_t>*"
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">(visitDefine_args(da));"))))))
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(add-before 'check 'prepare-tests
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(lambda* (#:key inputs #:allow-other-keys)
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;; Symlink yosys source for yosys testsuite.
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(delete-file-recursively "tests/yosys")
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(symlink (assoc-ref inputs "yosys-src-for-hdlconvertor-tests")
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"tests/yosys")
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;; Remove source hdlConvertor/ which shadows the installed package.
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(delete-file-recursively "hdlConvertor")
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;; Replace tests/__init__.py which imports all.py that requires
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;; git submodules; also delete tests requiring external tools.
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(call-with-output-file "tests/__init__.py"
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(lambda (port)
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(display "" port)))
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(delete-file "tests/all.py")
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(for-each delete-file
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(find-files "tests" "test_ghdl"))
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(for-each delete-file
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(find-files "tests" "test_icarus"))
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(for-each delete-file
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(find-files "tests" "test_verilator"))
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(for-each delete-file
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(find-files "tests" "test_uvvm"))
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(for-each delete-file
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(find-files "tests" "test_vunit"))
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(for-each delete-file
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(find-files "tests" "test_notebook"))
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(for-each delete-file
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(find-files "tests" "test_basic_hdl_sim")))))))
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(native-inputs
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(list antlr4 ; parser generator tool (antlr4.jar)
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antlr3 ; antlr3-runtime.jar required by hdlConvertor build
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java-antlr4-runtime ; antlr4-runtime.jar required by hdlConvertor build
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java-stringtemplate ; stringtemplate4.jar required by hdlConvertor build
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java-treelayout ; treelayout.jar required by hdlConvertor build
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(list openjdk "jdk") ; Java runtime to execute ANTLR4
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;;; Python build dependencies:
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python-cython ; compiles .pyx extension files to C++
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python-scikit-build ; CMake-based Python build system
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python-setuptools
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python-wrapper ; Python interpreter for build scripts
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python ; Python headers for C extension building
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python-pytest
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;; Yosys source for parsing tests.
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yosys-src-for-hdlconvertor-tests))
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(inputs
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(list java-antlr4-runtime-cpp))
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(propagated-inputs
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(list python-hdlconvertorast))
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(home-page "https://github.com/Nic30/hdlConvertor")
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(synopsis "VHDL and System Verilog parser")
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(description "This package provides a @acronym{VHDL, Very high speed
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integrated circuit Hardware Description Language} and SystemVerilog
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parser library for Python.")
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(license license:expat)))
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(define-public python-pyucis
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(package
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(name "python-pyucis")
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